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Conference Papers Year : 2016

Cross-layer system reliability assessment framework for hardware faults

Abstract

System reliability estimation during early design phases facilitates informed decisions for the integration of effective protection mechanisms against different classes of hardware faults. When not all system abstraction layers (technology, circuit, microarchitecture, software) are factored in such an estimation model, the delivered reliability reports must be excessively pessimistic and thus lead to unacceptably expensive, over-designed systems. We propose a scalable, cross-layer methodology and supporting suite of tools for accurate but fast estimations of computing systems reliability. The backbone of the methodology is a component-based Bayesian model, which effectively calculates system reliability based on the masking probabilities of individual hardware and software components considering their complex interactions. Our detailed experimental evaluation for different technologies, microarchitectures, and benchmarks demonstrates that the proposed model delivers very accurate reliability estimations (FIT rates) compared to statistically significant but slow fault injection campaigns at the microarchitecture level.

Dates and versions

lirmm-01444774 , version 1 (24-01-2017)

Identifiers

Cite

Alessandro Vallero, Alessandro Savino, Gianfranco Michele Maria Politano, Stefano Di Carlo, Athanasios Chatzidimitriou, et al.. Cross-layer system reliability assessment framework for hardware faults. ITC: International Test Conference, Nov 2016, Fort Worth, TX, United States. ⟨10.1109/TEST.2016.7805863⟩. ⟨lirmm-01444774⟩
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