Power management techniques are applied at high abstraction levels to reduce chip power consumption. Accurate and efficient power models are needed as early as possible in the design flow to ensure that correct saving decisions are taken. However, accuracy at those levels cannot be ensured, as there is not exact knowledge of the circuit structure. Then, power models based on estimation techniques at lower abstraction levels are desired. In this work, we propose a hybrid power modeling approach based on an effective library characterization methodology and an efficient power estimation flow to accurately assess gate-level power consumption. The main idea is to enhance the high-level power models by providing realistic information of the physical design. We perform experiments on ISCAS'85 benchmark circuits synthesized with a 28nm FDSOI technology. To prove the validity of our approach, we compare our results with SPECTRE simulations and show that we can achieve a 144X speedup on the runtime with a transistor-like accuracy.