An Effective Power-Aware At-Speed Test Methodology for IP Qualification and Characterization

Abstract : Advanced nanometer technologies have led to a drastic increase in operational frequencies resulting in the performance of circuits becoming increasingly vulnerable to timing variations. The increasing process spread in advanced nanometer nodes poses considerable challenges in predicting post-fabrication silicon performance from timing models. Thus, there is a great need to qualify basic building structures on silicon in terms of critical parameters before they could be integrated within a complex System-on-Chip (SoC). The work of this paper presents a configurable circuit and an associated power-aware at-speed test methodology for the purpose of qualifying basic standard cells and complex IP structures to detect the presence of timing faults. Our design has been embedded within test-chips used for the development of the 28 nm Fully Depleted Silicon On Insulator (FD-SOI) technology node. The relevant silicon results and analysis validate the proposed power-aware test methodology for qualification and characterization of IPs and provide deeper insights for process improvements.
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Article dans une revue
Journal of Electronic Testing, Springer Verlag, 2016, 32 (6), pp.721-733. 〈10.1007/s10836-016-5621-1〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-01446887
Contributeur : Caroline Lebrun <>
Soumis le : jeudi 26 janvier 2017 - 13:54:10
Dernière modification le : jeudi 28 juin 2018 - 18:44:01

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Kapil Juneja, Darayus Adil Patel, Rajesh Kumar Immadi, Balwant Singh, Sylvie Naudet, et al.. An Effective Power-Aware At-Speed Test Methodology for IP Qualification and Characterization. Journal of Electronic Testing, Springer Verlag, 2016, 32 (6), pp.721-733. 〈10.1007/s10836-016-5621-1〉. 〈lirmm-01446887〉

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