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Conference Papers Year : 2017

Scalable and Power-Efficient Implementation of an Asynchronous Router with Buffer Sharing

Charles Emmanuel Effiong
Gilles Sassatelli
Abdoulaye Gamatié

Abstract

Network-on-Chip provides scalable communication in Systems-on-Chip with many Intellectual Property cores. Studies have shown that unutilized router buffers lead to significant network performance degradation. This work presents Roundabout, a new asynchronous router architecture with inherent and effective buffer utilization. Inspired by real-life multi-lane roundabouts, it consists of lanes shared by input and output ports. A prototype of Roundabout is evaluated using 45nm CMOS technology. The router is able to achieve a throughput of 465 Mflit/sec. It achieves a network saturation threshold of 129 Gbps on a 4x4 Mesh topology network. Roundabout performance, area and power results are competitive with existing synchronous and asynchronous solutions. It provides good topological tradeoffs for significantly improving network performance without corresponding area overhead.
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Dates and versions

lirmm-01622885 , version 1 (24-10-2017)

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Charles Emmanuel Effiong, Gilles Sassatelli, Abdoulaye Gamatié. Scalable and Power-Efficient Implementation of an Asynchronous Router with Buffer Sharing. DSD: Digital System Design, Aug 2017, Vienna, Australia. pp.171-178, ⟨10.1109/DSD.2017.55⟩. ⟨lirmm-01622885⟩
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