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Conference papers

Distributed and Dynamic Shared-Buffer Router for High-Performance Interconnect

Charles Effiong 1 Gilles Sassatelli 1 Abdoulaye Gamatié 1
1 ADAC - ADAptive Computing
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : Most Network-on-Chip routers dedicate a set of buffers to the input and/or output ports. This design decision leads to buffer underutilization especially when running applications with non-uniform traffic patterns. In order to maximize resource usage for performance and energy gains, we present a synchronous and elastic buffer implementation of a router architecture called Roundabout with intrinsic resource sharing. Roundabout is inspired by real-life traffic roundabouts and consists of lanes shared by multiple input and output ports. Roundabout offers performance improvement of 61% for uniform traffic pattern and up to 88% for non-uniform traffic pattern over the Hermes router, a typical input buffered router. In terms of power, it consumes 24% less than the Hermes router. Roundabout provides a highly parametric architecture that can produce different router configurations with varying topological trade-offs for performance gains without sacrificing area.
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Contributor : Charles Effiong Connect in order to contact the contributor
Submitted on : Tuesday, October 24, 2017 - 5:38:09 PM
Last modification on : Wednesday, November 3, 2021 - 7:44:57 AM




Charles Effiong, Gilles Sassatelli, Abdoulaye Gamatié. Distributed and Dynamic Shared-Buffer Router for High-Performance Interconnect. NOCS: Networks-on-Chip Symposium, Oct 2017, Seoul, South Korea. pp.1-8, ⟨10.1145/3130218.3130223⟩. ⟨lirmm-01622889⟩



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