Method for evaluation of transient-fault detection techniques

Abstract : This work introduces a simulation-based method for evaluating the efficiency of detection techniques in identifying transient faults provoked in combinational logic blocks. Typical fault profiles are simulated in campaigns of injections that reproduce output scenarios of fault-affected combinational circuits. Furthermore, a detection technique is proposed and compared to state-of-the-art strategies by using the method presented herein. Results show the capabilities of all studied techniques, providing a rank in terms of their efficiencies in detecting transient faults induced in combinational logic circuits, and analyzing the situations in which soft errors are produced in memory elements.
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Article dans une revue
Microelectronics Reliability, Elsevier, 2017, 76-77, pp.68-74. 〈10.1016/j.microrel.2017.07.007〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-01690185
Contributeur : Philippe Maurine <>
Soumis le : lundi 22 janvier 2018 - 17:34:24
Dernière modification le : jeudi 7 février 2019 - 17:04:10

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Raphael Andreoni Camponogara-Viera, Rodrigo Possamai Bastos, Jean-Max Dutertre, Philippe Maurine, Rodrigo Iga Jadue. Method for evaluation of transient-fault detection techniques. Microelectronics Reliability, Elsevier, 2017, 76-77, pp.68-74. 〈10.1016/j.microrel.2017.07.007〉. 〈lirmm-01690185〉

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