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Impacts of Technology Trends on Physical Attacks?

Philippe Maurine 1 Sylvain Guilley 2
1 SmartIES - Smart Integrated Electronic Systems
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : Chip fabrication technologies evolve at an explosive rate. Notwithstanding, we analyze that attacks on smartcard chips are almost not impacted: only the architecture which gets more complex (e.g., the devices transition from mono- to multi-core) and the advanced design solutions (adaptative voltage and frequency scaling, multiple clock domains, asynchronicity, etc.) somehow make attacks slightly more complex. The situation is different for chips tightly integrated in embedded devices, such as smartphone chips. Indeed, the chips size and complexity increase drastically, and thus attacks identification phase becomes extremely hard. In addition, the chip targetted by the attacks is usually stacked with other chips (like the memory), which makes access to leakages and injection of faults a challenging task. Therefore, we conclude that there is a clear gain of security in the future to use smartphones as secure elements. Attacks at printed circuit board level associated with signal processing and machine learning could question this conclusion. Also, as a perspective, we notice that new kinds of attacks become possible on smartphones. Those devices being intrinsically connected, the new side-channel and fault injection attacks are realized not physically, but in software (controlled from an external center attack process): such attacks are called microarchitectural cache timing attacks (regarding side-channels) and RowHammer attacks (regarding fault injections). We predict increasing progress in those cyberattack threats.
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Contributor : Philippe Maurine <>
Submitted on : Monday, January 22, 2018 - 5:40:35 PM
Last modification on : Wednesday, June 24, 2020 - 4:19:13 PM



Philippe Maurine, Sylvain Guilley. Impacts of Technology Trends on Physical Attacks?. COSADE: Constructive Side-Channel Analysis and Secure Design, Apr 2017, Paris, France. pp.190-206, ⟨10.1007/978-3-319-64647-3_12⟩. ⟨lirmm-01690188⟩



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