A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic Circuits

Arnaud Virazel 1 Imran Wali 1 Bastien Deveautour 1 Alberto Bosio 1 Patrick Girard 1 M. Sonza Reorda 2
1 TEST - TEST
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : Selecting the ideal trade-off between reliability and cost associated with a fault tolerant architecture generally involves an extensive design space exploration. Employing state-of-the-art reliability estimation methods makes this exploration un-scalable with the design complexity. In this paper we introduce a low-cost reliability analysis methodology that helps taking this key decision with less computational effort and orders of magnitude faster. Based on this methodology we also propose a selective hardening technique using a hybrid fault tolerant architecture that allows meeting the soft-error rate constraints within a given design cost-budget and vice versa. Our experimental validation shows that the methodology offers huge gain (1200 ×) in terms of computational effort in comparison with fault injection-based reliability estimation method and produces results within acceptable error limits.
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-01718568
Contributor : Arnaud Virazel <>
Submitted on : Tuesday, February 27, 2018 - 2:59:53 PM
Last modification on : Wednesday, August 28, 2019 - 3:46:02 PM

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Arnaud Virazel, Imran Wali, Bastien Deveautour, Alberto Bosio, Patrick Girard, et al.. A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic Circuits. Journal of Electronic Testing, Springer Verlag, 2017, 33 (1), pp.25-36. ⟨10.1007/s10836-017-5640-6⟩. ⟨lirmm-01718568⟩

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