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Conference Papers Year : 2017

An effective fault-injection framework for memory reliability enhancement perspectives

Abstract

Embedded SRAM elements are becoming the main detractor of the overall System-on-Chip (SoC) yield. To increase the reliability of embedded SRAMs, the use of Error Correction Code (ECC) has been widely adopted. Depending on the implemented ECC scheme, SRAMs can detect/correct the presence of one or more transient errors during the mission time. In this paper, we investigate the possibility of exploiting the ECC for dealing with permanent faults due to physical defects in embedded SRAM. In this work, we present an effective fault-injection framework to inject static and dynamic faults and to determine their impact on a given ECC scheme. As case study, the target memory is a word-oriented SRAM including detection and correction codes. The proposed framework makes possible the evaluation of the SRAM behavior in the presence of different faulty scenarios. Injected faults involve single as well as multiple cells with static and dynamic behaviors.
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Dates and versions

lirmm-01718579 , version 1 (27-02-2018)

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Ghita Harcha, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi. An effective fault-injection framework for memory reliability enhancement perspectives. DTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2017, Palma de Mallorca, Spain. ⟨10.1109/DTIS.2017.7930172⟩. ⟨lirmm-01718579⟩
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