Synchronised 4-Phase Resonant Power Clock Supply for Energy Efficient Adiabatic Logic

Abstract : Adiabatic logic is an alternative architecture design style to reduce the power consumption of digital cores by using AC power supply instead of DC ones. The energy saving of the digital gates is strongly related to the efficiency of adiabatic AC power supplies. In this paper, we propose a resonant reversible power-clock supply design with four different phases. The resonance deviation between the four power-clock supplies is synchronized thanks to 12 control signals (3 controls signals per power-clock supply). We derive the energy dissipation of a 4-stage PFAL pipeline circuit supplied with the proposed resonant powerclock supply, which can dissipate up to 2.9 times less energy than a non-adiabatic CMOS pipeline.
Type de document :
Communication dans un congrès
ICRC: International Conference on Rebooting Computing, Nov 2017, Washington, DC, United States. IEEE, IEEE International Conference on Rebooting Computing, 2017, 〈10.1109/ICRC.2017.8123661〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-01768831
Contributeur : Pascal Nouet <>
Soumis le : mardi 17 avril 2018 - 14:49:51
Dernière modification le : lundi 11 février 2019 - 16:45:51

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Nicolas Jeanniot, Gael Pillonnet, Pascal Nouet, Nadine Azemard, Aida Todri-Sanial. Synchronised 4-Phase Resonant Power Clock Supply for Energy Efficient Adiabatic Logic. ICRC: International Conference on Rebooting Computing, Nov 2017, Washington, DC, United States. IEEE, IEEE International Conference on Rebooting Computing, 2017, 〈10.1109/ICRC.2017.8123661〉. 〈lirmm-01768831〉

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