Meta-implementation of vectorized logarithm function in binary floating-point arithmetic

Hugues De Lassus Saint-Geniès 1 Nicolas Brunie 2 Guillaume Revy 1
1 DALI - Digits, Architectures et Logiciels Informatiques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier, UPVD - Université de Perpignan Via Domitia
Abstract : Besides scalar instructions, modern micro-architectures also provide support for vector instructions. They enable to treat packed inputs (typically 4 or 8) in a single instruction. The challenge is now to write vector programs to support mathematical functions like sin, cos, exp, log, ··· which efficiently exploit those vector instructions. This article focuses on the design of vectorized implementation of log(x) function, and more particularly on its automation for different formats and micro-architectures. First it rewrites a classic range reduction in a branchless fashion so as to use at best recent micro-architecture features, like rcp (reciprocal) instruction, and to treat all inputs in the same flow. Second it details rigorously how to achieve “faithfully rounded” implementations. Third it shows how to automate this implementation process using the MetaLibm framework, on SSE/AVX and AVX2 supporting micro-architectures. Finally we illustrate that this process enables to achieve high throughput implementations for the binary32 and binary64 formats in a fully automated way.
Type de document :
Communication dans un congrès
ASAP: Application-specific Systems, Architectures and Processors, Jul 2018, Milan, Italy. 29th IEEE International Conference Application-specific Systems, Architectures and Processors, 2018, ASAP 2018. 〈https://asap18.necst.it〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-01840853
Contributeur : Guillaume Revy <>
Soumis le : lundi 16 juillet 2018 - 17:25:01
Dernière modification le : vendredi 20 juillet 2018 - 11:36:03

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  • HAL Id : lirmm-01840853, version 1

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Hugues De Lassus Saint-Geniès, Nicolas Brunie, Guillaume Revy. Meta-implementation of vectorized logarithm function in binary floating-point arithmetic. ASAP: Application-specific Systems, Architectures and Processors, Jul 2018, Milan, Italy. 29th IEEE International Conference Application-specific Systems, Architectures and Processors, 2018, ASAP 2018. 〈https://asap18.necst.it〉. 〈lirmm-01840853〉

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