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Conference Papers Year : 2017

Atomistic to circuit level modeling of defective doped SWCNTs with contacts for on-chip interconnect application

Abstract

Carbon nanotubes (CNTs) due to their high electrical/thermal conductivity, high ampacity, high tolerance to electro-migration [1] and small dimensions make them an ideal candidate for future on-chip interconnects [2]. Fabricating the CNTs, random chirality and some defects are introduced which can degrade the CNT electrical properties [3]. Additionally, the contact resistance between metal and CNT presents additional parasitics that impose restraints on the electron transport. Electrical models of CNT for interconnect application were developed several years ago [4-5]. In this paper, we explored on doped and defective single-wall CNTs (SWCNT (24,0)) including contact resistance as important physical parameters to assess the performance of fabricated SWCNTs realistically for back-end-of-line (BEOL) on-chip interconnects on VLSI circuit application.
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Dates and versions

lirmm-01880220 , version 1 (16-07-2019)

Identifiers

Cite

Jie Liang, Lee Jaehyun, Salim Berrada, Vihar P. Georgiev, Asenov Asen, et al.. Atomistic to circuit level modeling of defective doped SWCNTs with contacts for on-chip interconnect application. NMDC: Nanotechnology Materials and Devices Conference, Oct 2017, Singapore, Singapore. pp.66-67, ⟨10.1109/NMDC.2017.8350506⟩. ⟨lirmm-01880220⟩
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