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Journal Articles Microprocessors and Microsystems: Embedded Hardware Design Year : 2018

Exploration of a scalable and power-efficient asynchronous Network-on-Chip with dynamic resource allocation

Charles Emmanuel Effiong
Gilles Sassatelli
Abdoulaye Gamatié

Abstract

Networks-on-Chip (NoCs) are now being used to provide inter-core communication for manycore Systems-on-Chip (SoCs). This is because traditional on-chip interconnects do not scale with increasing number of cores. Typical NoCs dedicate a set of buffers to their input and/or output ports. This can lead to buffer under-utilization for applications with non-uniform traffic characteristics. In order to provide improved buffer utilization for performance gains and energy efficiency, we have proposed the Roundabout-NoC (R-NoC) concept. R-NoC is inspired by real-life multi-lane traffic roundabouts. It consists of lanes shared by multiple input/output ports. This allows the buffers to be exploited for performance gains by data-flows from multiple input ports. This work extends the asynchronous evaluation of the R-NoC, named R-NoC-A. The router is evaluated using 45 nm CMOS technology. The R-NoC-A router achieves a throughput of 465 Mflit/s and a network saturation throughput of 129 Gbps on a 4 × 4 mesh network. R-NoC-A results, in terms of performance, area and power consumption, are highly competitive to existing solutions (synchronous and asynchronous). It provides good topological trade-offs for significantly improving network performance without corresponding area overhead.
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Dates and versions

lirmm-01912679 , version 1 (05-11-2018)

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Charles Emmanuel Effiong, Gilles Sassatelli, Abdoulaye Gamatié. Exploration of a scalable and power-efficient asynchronous Network-on-Chip with dynamic resource allocation. Microprocessors and Microsystems: Embedded Hardware Design , 2018, 60, pp.173-184. ⟨10.1016/j.micpro.2018.05.003⟩. ⟨lirmm-01912679⟩
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