FinFET technology has become the most promising alternative to continue CMOS scaling. However, Finfet design makes use of complex interconnect structures (e.g middle-of-line -MOL- interconnections), and multi-fin and multi-finger devices, which pose a challenge to test open defects. In this paper, open defects at gate locations in FinFET based cells are investigated. The parasitic capacitances of the cells are extracted using Raphael 3D Field Solver. The logic and dynamic behavior of the opens defects is analyzed, and possible defective topologies are defined. Some open locations present behaviors similar to those presented in planar CMOS based circuits. However, most of the open locations present new subtle behaviors. The use of multi-fin and multi-finger devices makes the opens more difficult to detect than in planar CMOS technology and non-detectable opens may pose reliability issues. Hence, a good understanding of the defect behavior is needed in order to develop new test strategies for FinFET based logic circuits to have circuits with higher quality.