We present a reliability study of power grids in power-gated chips. We investigate those conditions that cause electromigration (EM) problems on the top metal layers as well as in local power grid meshes. Also, we identify the potential EM constraint violating branches and vias by observing their current flow under various power gating conditions. Power supply noise, process and thermal variations are some of the factors that can also affect EM in power grid branches and vias. Our study shows that a power grid network optimized for all blocks working may experience EM problems when power gating is applied.