Evaluation of the temperature influence on SEU vulnerability of DICE and 6T-SRAM cells

Emna Farjallah 1, 2 Valentin Gherman 1 Jean-Marc Armani 1 Luigi Dilillo 2
1 LRI - Laboratoire de Robotique Interactive
DIASI - Département Intelligence Ambiante et Systèmes Interactifs : DRT/LIST/DIASI
2 TEST - TEST
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : In this paper, we evaluate the temperature influence on the vulnerability to single event upsets (SEU) of 6-transistor static random access memory (6T-SRAM) cells and dual interlocked storage cells (DICE). The critical charge (Qcrit, minimum charge capable of generating an SEU) is evaluated for 65nm, 45nm, 32nm and 22nm bulk CMOS technologies and temperatures between -50°C and 150°C. A double exponential signal is used to model the current pulse generated by ionizing particles. SPICE simulations have shown that Qcrit is sensibly reduced by the rise of temperature. Qcrit variations of up to 88.4% and 99.9% have been calculated for 6T-SRAM and DICE cells, respectively.
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-02008214
Contributor : Luigi Dilillo <>
Submitted on : Tuesday, February 5, 2019 - 3:46:27 PM
Last modification on : Thursday, July 25, 2019 - 3:40:23 PM

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Emna Farjallah, Valentin Gherman, Jean-Marc Armani, Luigi Dilillo. Evaluation of the temperature influence on SEU vulnerability of DICE and 6T-SRAM cells. DTIS: Design & Technology of Integrated Systems In Nanoscale Era, LIRMM, Apr 2018, Taormina, Italy. ⟨10.1109/DTIS.2018.8368578⟩. ⟨lirmm-02008214⟩

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