This paper deals with the analysis of the impact of process variations on the detection of resistive short defects, in the context of a logic-based test. Two types of short defects are considered for our investigation, i.e. resistive short to either ground terminal (GND) or power supply terminal (VDD). For both defect types, simple analytical models are proposed that permit to evaluate the robust detectability range in presence of process variations. These models rely on a pre-characterization of the gate library through Monte-Carlo simulation and permit to evaluate the detectability range of a given defect without performing any fault simulation. These models are applied to perform a comparative analysis of 28 nm Bulk and FDSOI (Fully Depleted Silicon-On-Insulator) technologies, considering both regular-VT and low-VT devices. The influence of operating conditions on defect detectability range is also investigated.