Design and Evaluation of a 28-nm FD-SOI STT-MRAM for Ultra-Low Power microcontrollers

Guillaume Patrigeon 1 Pascal Benoit 1 Lionel Torres 1 Sophiane Senni 1 Guillaume Prenat 2 Gregory Di Pendina 2
1 ADAC - ADAptive Computing
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : The complexity of embedded devices increases as today's applications request always more services. However, the power consumption of systems-on-chip has significantly increased due to the high-density integration and the high leakage power of current CMOS transistors. To address these issues, emerging technologies are considered. Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) is seen as a promising alternative solution to traditional memories thanks to its negligible leakage current, high density, and non-volatility. In this work, we present the design and evaluation of a 128 kB STT-RAM in 28-nm FD-SOI technology with SRAM-like interface for ultra-low power microcontrollers. With 0.9 pJ/bit read in 5 ns and 3 pJ/bit write in 10 ns, this embedded non-volatile memory is suitable for devices that run at frequencies under 100 MHz. Considering low-power application with duty-cycled behaviour, we evaluate the STT-MRAM as a replacement of embedded Flash and SRAM by comparing single and multi-memory architecture scenarios.
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Contributor : Guillaume Patrigeon <>
Submitted on : Monday, May 13, 2019 - 5:40:19 PM
Last modification on : Tuesday, May 14, 2019 - 10:35:57 AM


Design and Evaluation of a 28-...
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Guillaume Patrigeon, Pascal Benoit, Lionel Torres, Sophiane Senni, Guillaume Prenat, et al.. Design and Evaluation of a 28-nm FD-SOI STT-MRAM for Ultra-Low Power microcontrollers. IEEE Access, IEEE, In press, 7, pp.58085-58093. ⟨10.1109/ACCESS.2019.2906942⟩. ⟨lirmm-02079679⟩



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