In today's electronic designs, more and more memories are embedded in a single chip. The latest technologies make them denser and thus defects due to the manufacturing process are more prone to occur not only in the array but also in the periphery of the memory. A fast and accurate localization of such defects has become much more difficult with traditional diagnosis approaches that do not allow a fast-enough yield learning and improvement. This paper describes a new and automated intra-cell diagnosis flow for SRAMs to precisely determine the root cause of observed failures during test. Based on the electrical and topological fault signatures obtained through traditional methods, each potential fault on the identified active nets is automatically simulated to retrieve the best defect candidates to precisely guide the Failure Analysis phase. The proposed intra-cell diagnosis flow has been experimented on simulated test cases as well as silicon (industrial) test cases. The results obtained demonstrate the effectiveness of the diagnosis flow in terms of low number of defect candidates. Moreover, for the silicon test cases, these diagnosis results match with the ongoing Failure Analysis reports.