Logic Locking: A Survey of Proposed Methods and Evaluation Metrics - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Journal Articles Journal of Electronic Testing: : Theory and Applications Year : 2019

Logic Locking: A Survey of Proposed Methods and Evaluation Metrics

Abstract

The outsourcing business model is dominating the semiconductor industry. Due to this loss of control over the design flow, several threats have become a major source of concern, including overproduction and IP overuse. For over a decade, several solutions have been proposed in the literature to counteract such threats. These solutions consist in hiding the behavior of the IPs/ICs until the design house securely unlocks them. This way, only unlocked IPs/ICs can be used properly while locked ones produce erroneous data. In this paper, we survey logic locking approaches and discuss locking quality in hiding expected behavior and in resisting to attacks.
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lirmm-02128826 , version 1 (14-05-2019)

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Sophie Dupuis, Marie-Lise Flottes. Logic Locking: A Survey of Proposed Methods and Evaluation Metrics. Journal of Electronic Testing: : Theory and Applications, 2019, 35 (3), pp.273-291. ⟨10.1007/s10836-019-05800-4⟩. ⟨lirmm-02128826⟩
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