Physical Design Challenges and Solutions for 3D Stacked and Monolithic 3D Integration -
This tutorial aims to provide an in-depth look into process, integration and design methods for 3D ICs. As first, an overview of 3D stacked ICs, and their physical design challenges with respect to conventional 2D circuits will be provided, followed by an in-depth look into the power and thermal integrity challenges and solutions [1-12]. More specifically, design challenges related to power, signal and clock distribution will be covered and also present some of the current solutions. Secondly, an overview of physical design challenges for monolithic 3D integration will be provided, and the differences with respect to 3D stacked ICs. The focus will be on power delivery for monolithic 3D ICs [13-14]. The tutorial will conclude with current challenges and future directions for 3D physical design.
The semiconductor industry enters the post Moore era where transistor scaling is not the sole driving force in delivering the required performance and functionality. To harvest the gains of higher integration densities without shrinking the feature size, monolithic three-dimensional (3D) integration has been proposed as a highly promising alternative to lead system integration in the post Moore regime. This tutorial aims to introduce this emerging technology from the perspectives of fabrication process, design automation, reliable and low power design, and architecutre innovations.