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Poster communications

A Hardware-aware Heuristic for the Qubit Mapping Problem in the NISQ Era

Abstract : Today’s quantum computers are qualified as noisy intermediate-scale quantum (NISQ) hardware with several physical limitations in the realization of quantum hardware. NISQ hardware is characterized by a small number of qubits (50 to a few hundred) and has noisy operations. Moreover, current superconducting quantum chips can only realize a nearest-neighbor connectivity between qubits rather than an ideal all-to-all connectivity. All these hardware constraints add supplementary requirements and they need to be addressed before executing quantum circuits on real quantum hardware. In our paper, we aim to solve the problem of adapting the quantum circuit to given hardware. We propose a hardware-aware (HA) mapping transition algorithm that takes the calibration data into account to improve the overall fidelity of the circuit. Evaluation results on IBM quantum hardware show that our HA approach can outperform the state of the art both in terms of the number of additional gates and circuit fidelity.
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-03275340
Contributor : Siyuan Niu Connect in order to contact the contributor
Submitted on : Thursday, July 1, 2021 - 8:52:59 AM
Last modification on : Friday, October 22, 2021 - 3:07:43 PM
Long-term archiving on: : Saturday, October 2, 2021 - 6:25:28 PM

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  • HAL Id : lirmm-03275340, version 1

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Siyuan Niu, Adrien Suau, Gabriel Staffelbach, Aida Todri-Sanial. A Hardware-aware Heuristic for the Qubit Mapping Problem in the NISQ Era. 15ème Colloque National du GDR SOC2, Jun 2021, Rennes, France. ⟨lirmm-03275340⟩

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