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Reliability analysis of a fault-tolerant RISC-V system-on-chip

Douglas Almeida dos Santos 1, 2 Lucas Matana Luza 2 Luigi Dilillo 2 Cesar Albenes Zeferino 1 Douglas Rossi Melo 1
2 TEST - TEST
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : The space environment's hostility requires that the processors used in spacecraft be designed using fault tolerance techniques to reduce the propagation of errors. In this context, this work presents a low-cost fault-tolerant processor based on the RISC-V architecture, an emerging industry standard for building embedded processors. The implemented processor was integrated with a System-on-Chip to assess the cost and efficiency of fault tolerance techniques at the processor and system levels through simulation of fault injection campaigns. The proposed implementation uses physical and information redundancy to reduce the propagation of errors. The processor has a low overhead in silicon compared to other implementations of the same architecture. It mitigates 100% of the single transient faults injected and more than 65% of the transient faults when multiple faults are injected at random moments and locations. The number of errors propagated is slightly higher at the system level because the other system's components are not protected.
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-03358839
Contributor : Luigi Dilillo Connect in order to contact the contributor
Submitted on : Wednesday, September 29, 2021 - 4:23:39 PM
Last modification on : Friday, October 22, 2021 - 3:07:43 PM

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Douglas Almeida dos Santos, Lucas Matana Luza, Luigi Dilillo, Cesar Albenes Zeferino, Douglas Rossi Melo. Reliability analysis of a fault-tolerant RISC-V system-on-chip. Microelectronics Reliability, Elsevier, 2021, 125, pp.#114346. ⟨10.1016/j.microrel.2021.114346⟩. ⟨lirmm-03358839⟩

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