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Article Dans Une Revue IEEE Transactions on Very Large Scale Integration (VLSI) Systems Année : 2021

DOVA PRO: A Dynamic Overwriting Voltage Adjustment Technique for STT-MRAM L1 Cache Considering Dielectric Breakdown Effect

Résumé

Physical Unclonable Function (PUF) attracts enormous attention in recent years to securely preserve confidential information in computing systems. The conventional PUFs require many independent PUF components and/or are incapable of generating multiple response-bit per cycle, resulting in significant area overhead and power consumption. Recently, spin-transfer torque magnetic cell (STT-mCell) has emerged as a promising spintronic device to be used in Computing-In-Memory (CIM) system. However, it is challenging to guarantee the hardware security of STT-mCell based circuits. In this work, we propose a novel STT-mCell Delay based PUF design (SD-PUF) exploiting the unique manufacturing process variation (PV) of STT-mCell that can overcome these issues. A methodology is used to select appropriate logic gates in the all-spin chip to generate a unique identification key. A linear feedback shift register (LFSR) initiates SD-PUF and simultaneously generates a 64-bit signature at each clock cycle. Bit generation in SD-PUF is stabilized using an automatic write-back technique. For uniqueness enhancements, a masking scheme is applied for signature improvement. The uniqueness of the improved SD-PUF is 49.61%. With ±20% supply voltage, and 5 • C-105 • C temperature variations, SD-PUF shows a strong resiliency. In comparison with the state-of-the-art PUFs, our approach can reduce hardware overhead and energy consumption effectively. Finally, the robustness of SD-PUF against various attacks is verified as well.
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Dates et versions

lirmm-03376949 , version 1 (13-10-2021)

Identifiants

Citer

Kangwei Xu, Dongrong Zhang, Patrick Girard, Qiang Ren, Yuanqing Cheng. DOVA PRO: A Dynamic Overwriting Voltage Adjustment Technique for STT-MRAM L1 Cache Considering Dielectric Breakdown Effect. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2021, 29 (7), pp.1325-1334. ⟨10.1109/TVLSI.2021.3073415⟩. ⟨lirmm-03376949⟩
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