Cost-Optimized and Robust Latch Hardened against Quadruple Node Upsets for Nanoscale CMOS - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Conference Papers Year : 2022

Cost-Optimized and Robust Latch Hardened against Quadruple Node Upsets for Nanoscale CMOS

Aibin Yan
Jie Cui
Zhengfeng Huang
Tianming Ni
Xiaoqing Wen

Abstract

With the aggressive reduction of CMOS transistor feature sizes, the soft error rate of nano-scale integrated circuits increases exponentially. In this paper, we propose a novel cost-optimized and robust latch, namely CRLHQ, hardened against quadruple-node-upsets (QNUs) for nanoscale CMOS technologies. The latch mainly comprises a 5×5 matrix based on interlocked source-drain cross-coupled inverters to robustly store logic values. Owing to the redundant constructed feedback loops, the latch can recover from all possible QNUs. Simulation results demonstrate all key QNUs' recovery of the proposed CRLHQ latch. Simulation results also show that the proposed latch can approximately reduce the D-Q delay by 44.3%, the silicon area by 7.3% and the delay-area-power product (DAPP) by 14.2%, compared with the state-of-the-art same-type reference latches that can recover from any QNU.
Fichier principal
Vignette du fichier
CO89.pdf (919.37 Ko) Télécharger le fichier
Origin : Files produced by the author(s)

Dates and versions

lirmm-03770182 , version 1 (06-09-2022)

Identifiers

Cite

Aibin Yan, Shukai Song, Jixiang Zhang, Jie Cui, Zhengfeng Huang, et al.. Cost-Optimized and Robust Latch Hardened against Quadruple Node Upsets for Nanoscale CMOS. ITC-Asia 2022 - IEEE International Test Conference in Asian, Aug 2022, Taipei, Taiwan. pp.73-78, ⟨10.1109/ITCAsia55616.2022.00023⟩. ⟨lirmm-03770182⟩
24 View
103 Download

Altmetric

Share

Gmail Facebook X LinkedIn More