Analysis of Read Port Short Defects in an 8T SRAM-based IMC Architecture - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Conference Papers Year :

Analysis of Read Port Short Defects in an 8T SRAM-based IMC Architecture

Abstract

A promising new alternative to efficiently solve the von Neumann bottleneck problem is to adopt In-Memory Computing (IMC) architectures. Beyond the arithmetic operations, IMC architectures aim at integrating additional logic operators directly in the memory array or/and at the periphery in order to provide close computing abilities. However, they are subject to manufacturing defects in the same way as conventional memories. In this paper, a comprehensive model of a 128x128 bitcell array based on 28nm FD-SOI process technology has been considered to analyze the behavior of IMC 8T SRAM bitcells in the presence of short defects injected in the read port. A hierarchical analysis allowing a thorough study of each defect has been carried in order to identify their impact in both memory and computing modes, locally on the defective bitcell as well as globally on the array.
Fichier principal
Vignette du fichier
GdR22_AMMOURA_Lila.pdf (939.7 Ko) Télécharger le fichier
Origin : Files produced by the author(s)

Dates and versions

lirmm-03990078 , version 1 (15-02-2023)

Identifiers

  • HAL Id : lirmm-03990078 , version 1

Cite

Lila Ammoura, Marie-Lise Flottes, Patrick Girard, Jean-Philippe Noel, Arnaud Virazel. Analysis of Read Port Short Defects in an 8T SRAM-based IMC Architecture. 16e Colloque National du GDR SoC², Jun 2022, Strasbourg, France. ⟨lirmm-03990078⟩
8 View
10 Download

Share

Gmail Facebook Twitter LinkedIn More