As the demand for denser and faster electronics is growing, semiconductor industry has responded by aggressively scaling transistor sizes to several nanometers. Nano-scale devices provide higher density circuits while imposing crucial power, thermal and reliability problems to the system. As wire width continue to shrink, copper interconnects in high-performance systems will suffer from significant increase in resistivity due to surface roughness and grain boundary scattering resulting in electromigration issues. Furthermore, as technology scaling following Moore’s law is reaching its limits, 3D integration is a novel, promising and fast-emerging technology. 3D integration provides several advantages over 2D ICs by enabling, higher functionality, small form factor and heterogeneous implementation. The work presented in the HDR manuscript addresses the challenges of designing reliable and energy efficient circuits and systems for emerging technologies. It covers: -modeling and simulation for understanding the physical, electrical and thermal behavior on 3D integrated circuits. -physical design methods for power and signal integrity of 3D integrated circuits. -energy efficiency exploration on circuits based on carbon nanotube (CNT) interconnects.