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Embedded Flash Testing: Overview and Perspectives

Abstract : The evolution of System-on-Chip (SoC) designs involves the development of non-volatile memory technologies like Flash. Embedded flash (eFlash) memories are based on the floating-gate transistor concept and can be subject to complex hard defects creating functional faults. In this paper, we present a complete analysis of a particular failure mechanism, referred as disturb phenomenon. Moreover, we analyze the efficiency of a particular test sequence to detect this disturb phenomenon. Finally we conclude on the interest to develop new test infrastructure well adapted to the eFlash environment
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00093665
Contributor : Martine Peridier <>
Submitted on : Wednesday, September 13, 2006 - 4:01:45 PM
Last modification on : Wednesday, August 28, 2019 - 3:46:02 PM
Long-term archiving on: : Monday, April 5, 2010 - 11:40:37 PM

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  • HAL Id : lirmm-00093665, version 1

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Olivier Ginez, Jean-Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, et al.. Embedded Flash Testing: Overview and Perspectives. DTIS: Design and Technology of Integrated Systems in Nanoscale Era, Sep 2006, Tunis, Tunisia. pp.210-215. ⟨lirmm-00093665⟩

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