Embedded Flash Testing: Overview and Perspectives

Abstract : The evolution of System-on-Chip (SoC) designs involves the development of non-volatile memory technologies like Flash. Embedded flash (eFlash) memories are based on the floating-gate transistor concept and can be subject to complex hard defects creating functional faults. In this paper, we present a complete analysis of a particular failure mechanism, referred as disturb phenomenon. Moreover, we analyze the efficiency of a particular test sequence to detect this disturb phenomenon. Finally we conclude on the interest to develop new test infrastructure well adapted to the eFlash environment
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Communication dans un congrès
IEEE. DTIS: Design and Technology of Integrated Systems in Nanoscale Era, Sep 2006, Tunis, Tunisia. pp.210-215, 2006
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Soumis le : mercredi 13 septembre 2006 - 16:01:45
Dernière modification le : jeudi 24 mai 2018 - 15:59:24
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  • HAL Id : lirmm-00093665, version 1

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Olivier Ginez, Jean-Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, et al.. Embedded Flash Testing: Overview and Perspectives. IEEE. DTIS: Design and Technology of Integrated Systems in Nanoscale Era, Sep 2006, Tunis, Tunisia. pp.210-215, 2006. 〈lirmm-00093665〉

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