Delay Testing Viability of Gate Oxide Short Defect

Jean-Marc Galliere 1 Michel Renovell 1 Florence Azaïs 1 Yves Bertrand 1
1 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : Gate Oxide Short (GOS) defects are becoming predominant as technology is scaling down. Boolean and I DDQ testing of this defect has been widely studied but there is no paper dedicated to delay testing of this defect. So, this paper studies the delay behavior of Gate Oxide Short faults due to pinhole in the gate oxide. The objective of this paper is to give a detailed analysis of the behavior of the GOS defect taking into account the random parameter of the defect such as the GOS resistance and the GOS location. Because an accurate analysis is desired, the bi-dimensional array will be used. Because a complete analysis is desired, we derive the dynamic characteristic of the GOS as a function of the GOS resistance and location. It is demonstrated that i) GOS has a significant impact on gate delay, ii) GOS located close to the source of the transistor and with small resistance has very high impact.
Keywords : VLSI
Type de document :
Article dans une revue
Journal of Computer Science and Technology, Iberoamerican Science & Technology Education Consortium, 2005, 20 (2), pp.195-200. 〈10.1007/s11390-005-0195-x〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00105323
Contributeur : Christine Carvalho de Matos <>
Soumis le : mercredi 11 octobre 2006 - 07:51:26
Dernière modification le : vendredi 20 juillet 2018 - 12:34:01

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Jean-Marc Galliere, Michel Renovell, Florence Azaïs, Yves Bertrand. Delay Testing Viability of Gate Oxide Short Defect. Journal of Computer Science and Technology, Iberoamerican Science & Technology Education Consortium, 2005, 20 (2), pp.195-200. 〈10.1007/s11390-005-0195-x〉. 〈lirmm-00105323〉

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