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Conference Papers Year : 2005

Test Application Time Reduction with a Dynamically Reconfigurable Scan Tree Architecture

Abstract

A dynamically reconfigurable scan tree architecture is proposed to reduce (up to 95%) test application time and test data volume of standard scan architectures. Additional important aspects, such as the impact of the new architecture on circuit performance and DFT area, are also considered in this paper.

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Dates and versions

lirmm-00105987 , version 1 (28-11-2020)

Identifiers

  • HAL Id : lirmm-00105987 , version 1

Cite

Yannick Bonhomme, Tomokazu Yoneda, Hideo Fujiwara, Patrick Girard. Test Application Time Reduction with a Dynamically Reconfigurable Scan Tree Architecture. 8th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS), Apr 2005, Sopron, Hungary. pp.19-26. ⟨lirmm-00105987⟩
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