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Physics and Design Optimization of ESD Diode for 0.13mm PD-SOI Technology

Abstract : This paper investigates the physics of 0.13 mum partially depleted SOI gated diodes through TLP measurements and TCAD simulations. The impact of gate length, well type, oxide thickness, gate to contact distance and presence of gate on ESD performance are evaluated and discussed. It is shown that the gate coupling effect decreases ESD performance.
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00106041
Contributor : Christine Carvalho de Matos <>
Submitted on : Friday, October 13, 2006 - 10:22:59 AM
Last modification on : Thursday, May 24, 2018 - 3:59:25 PM

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  • HAL Id : lirmm-00106041, version 1

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Christophe Entringer, Philippe Flatresse, Pascal Salomé, Pascal Nouet, Florence Azaïs. Physics and Design Optimization of ESD Diode for 0.13mm PD-SOI Technology. EOS/ESD: Electrical Overstress/Electrostatic Discharge, Sep 2005, Anaheim, United States. ⟨lirmm-00106041⟩

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