Physics and Design Optimization of ESD Diode for 0.13mm PD-SOI Technology - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Conference Papers Year : 2005

Physics and Design Optimization of ESD Diode for 0.13mm PD-SOI Technology

Abstract

This paper investigates the physics of 0.13 mum partially depleted SOI gated diodes through TLP measurements and TCAD simulations. The impact of gate length, well type, oxide thickness, gate to contact distance and presence of gate on ESD performance are evaluated and discussed. It is shown that the gate coupling effect decreases ESD performance.
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Dates and versions

lirmm-00106041 , version 1 (13-10-2006)

Identifiers

  • HAL Id : lirmm-00106041 , version 1

Cite

Christophe Entringer, Philippe Flatresse, Pascal Salomé, Pascal Nouet, Florence Azaïs. Physics and Design Optimization of ESD Diode for 0.13mm PD-SOI Technology. EOS/ESD: Electrical Overstress/Electrostatic Discharge, Sep 2005, Anaheim, United States. ⟨lirmm-00106041⟩
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