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Power-Aware Scan Testing for Peak Power Reduction

Nabil Badereddine 1 Patrick Girard 1 Serge Pravossoudovitch 1 Arnaud Virazel 1 Christian Landrault 1 
1 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
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Conference papers
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00106112
Contributor : Christine Carvalho De Matos Connect in order to contact the contributor
Submitted on : Friday, October 13, 2006 - 10:23:14 AM
Last modification on : Friday, August 5, 2022 - 10:48:03 AM

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  • HAL Id : lirmm-00106112, version 1

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CNRS | SYSMIC | LIRMM | LIRMM_MIC | MIC | MIPS | UNIV-MONTPELLIER

Citation

Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Christian Landrault. Power-Aware Scan Testing for Peak Power Reduction. VLSI-SOC'05: IFIP International Conference on Very Large Scale Integration, Oct 2005, Perth, Australia. pp.441-446. ⟨lirmm-00106112⟩

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