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Path Optimization Protocol Based on Speed Low Power Metrics

Abstract : The design of high performance circuits implies to manage CAD tools with physical level defined indicators. In this paper, we validate a design space exploration method, defining maximum and minimum delay bounds on logical paths. Then we adapt this method to a "constant sensitivity method" allowing to size a circuit at minimum area under a delay constraint. Three techniques are characterized: path global sizing, local buffer insertion and mixed sizing and buffer insertion. These methods are implemented in an optimization tool and compared on ISCAS'85 benchmarks with an industrial tool.
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Contributor : Christine Carvalho de Matos Connect in order to contact the contributor
Submitted on : Monday, October 16, 2006 - 8:00:13 AM
Last modification on : Friday, October 22, 2021 - 3:07:36 PM




Alexandre Verle, Alexis Landrault, Philippe Maurine, Nadine Azemard. Path Optimization Protocol Based on Speed Low Power Metrics. EUROCON: International Conference on "Computer as a Tool", Nov 2005, Belgrade, Serbia. pp.523-526, ⟨10.1109/EURCON.2005.1629980⟩. ⟨lirmm-00106428⟩



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