Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing

Abstract : Scan architectures, though widely used in modern designs for testing purpose, are expensive in power consumption. In this paper, we first discuss the issues of excessive peak power consumption during scan testing. We next show that taking care of high current levels during the test cycle (i.e. between launch and capture) is highly relevant so as to avoid noise phenomena such as IR-drop or Ground Bounce. Then, we propose a solution based on power-aware assignment of don't care bits in deterministic test patterns that considers structural information of the circuit under test. Experiments have been performed on ISCAS'89 and ITC'99 benchmark circuits with the proposed structural-based poweraware X-filling technique. These results show that the proposed technique provides the best tradeoff between peak power reduction and increase of test sequence lenght.
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Communication dans un congrès
VLSI-SOC'06: 14th IFIP WG 10.5 International Conference on Very Large Scale Integration and System-on-Chip, Oct 2006, Nice (France), IEEE, pp.403-408, 2006
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Soumis le : jeudi 19 octobre 2006 - 16:43:28
Dernière modification le : jeudi 24 mai 2018 - 15:59:24
Document(s) archivé(s) le : mardi 6 avril 2010 - 20:14:08

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  • HAL Id : lirmm-00108141, version 1

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Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Christian Landrault, Arnaud Virazel, et al.. Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing. VLSI-SOC'06: 14th IFIP WG 10.5 International Conference on Very Large Scale Integration and System-on-Chip, Oct 2006, Nice (France), IEEE, pp.403-408, 2006. 〈lirmm-00108141〉

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