Security Evaluation of Dual Rail Logic Against DPA Attacks

Abstract : Based on a first order model of the switching current flowing in CMOS cell, an investigation of the robustness against DPA attacks of dual rail logic is carried out. The result of this investigation, performed on 130nm process, is the formal identification of the design range in which dual rail logic can be considered as robust.
Type de document :
Communication dans un congrès
VLSI-SOC'06: 14th IFIP WG 10.5 International Conference on Very Large Scale Integration and System-On-Chip, Oct 2006, Nice (France), IEEE, pp.181-186, 2006
Liste complète des métadonnées

https://hal-lirmm.ccsd.cnrs.fr/lirmm-00109692
Contributeur : Martine Peridier <>
Soumis le : mercredi 25 octobre 2006 - 12:36:36
Dernière modification le : lundi 25 juin 2018 - 16:02:55
Document(s) archivé(s) le : mardi 6 avril 2010 - 20:56:22

Identifiants

  • HAL Id : lirmm-00109692, version 1

Collections

Citation

Hanitriniaina Razafindraibe, Philippe Maurine, Michel Robert, Marc Renaudin. Security Evaluation of Dual Rail Logic Against DPA Attacks. VLSI-SOC'06: 14th IFIP WG 10.5 International Conference on Very Large Scale Integration and System-On-Chip, Oct 2006, Nice (France), IEEE, pp.181-186, 2006. 〈lirmm-00109692〉

Partager

Métriques

Consultations de la notice

237

Téléchargements de fichiers

182