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Conference Papers Year : 2006

Security Evaluation of Dual Rail Logic Against DPA Attacks

Abstract

Based on a first order model of the switching current flowing in CMOS cell, an investigation of the robustness against DPA attacks of dual rail logic is carried out. The result of this investigation, performed on 130nm process, is the formal identification of the design range in which dual rail logic can be considered as robust.
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Dates and versions

lirmm-00109692 , version 1 (25-10-2006)

Identifiers

Cite

Hanitriniaina Razafindraibe, Philippe Maurine, Michel Robert, Marc Renaudin. Security Evaluation of Dual Rail Logic Against DPA Attacks. VLSI-SoC 2006 - 14th IFIP International Conference on Very Large Scale Integration, Oct 2006, Nice, France. pp.181-186, ⟨10.1109/VLSISOC.2006.313230⟩. ⟨lirmm-00109692⟩
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