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Security Evaluation of Dual Rail Logic Against DPA Attacks

Abstract : Based on a first order model of the switching current flowing in CMOS cell, an investigation of the robustness against DPA attacks of dual rail logic is carried out. The result of this investigation, performed on 130nm process, is the formal identification of the design range in which dual rail logic can be considered as robust.
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00109692
Contributor : Martine Peridier <>
Submitted on : Wednesday, October 25, 2006 - 12:36:36 PM
Last modification on : Friday, December 11, 2020 - 8:28:03 AM
Long-term archiving on: : Tuesday, April 6, 2010 - 8:56:22 PM

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  • HAL Id : lirmm-00109692, version 1

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Hanitriniaina Razafindraibe, Philippe Maurine, Michel Robert, Marc Renaudin. Security Evaluation of Dual Rail Logic Against DPA Attacks. VLSI-SOC'06: 14th IFIP WG 10.5 International Conference on Very Large Scale Integration and System-On-Chip, Oct 2006, Nice (France), pp.181-186. ⟨lirmm-00109692⟩

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