Formal Evaluation of the Robustness of Dual-Rail Logic Against DPA Attacks

Abstract : Based on a first order model of the switching current flowing in CMOS cell, an investigation of the robustness against DPA of dual-rail logic is carried out.
Type de document :
Chapitre d'ouvrage
Nadine Azémard, Philippe Maurine, Johan Vounckx. Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 4148/2006, Springer Berlin / Heidelberg, pp.634-644, 2006, Lecture Notes in Computer Science, 978-3-540-39094-7. 〈10.1007/11847083_44〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00109844
Contributeur : Martine Peridier <>
Soumis le : mercredi 25 octobre 2006 - 16:43:07
Dernière modification le : mardi 26 juin 2018 - 01:18:36

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Hanitriniaina Razafindraibe, Michel Robert, Philippe Maurine. Formal Evaluation of the Robustness of Dual-Rail Logic Against DPA Attacks. Nadine Azémard, Philippe Maurine, Johan Vounckx. Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 4148/2006, Springer Berlin / Heidelberg, pp.634-644, 2006, Lecture Notes in Computer Science, 978-3-540-39094-7. 〈10.1007/11847083_44〉. 〈lirmm-00109844〉

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