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Power-Aware Test Data Compression for Embedded IP Core

Résumé : Scan architectures, though widely used in modern designs for testing purpose, are expensive in test data volume and power consumption. To solve these problems, we propose in this paper to modify an existing test data compression technique [1] so that it can simultaneously address test data volume and power consumption reduction for scan testing of embedded Intellectual Property (IP) cores. Compared to the initial solution that fill don't-care bits with the aim of reducing only test data volume, here the assignment is performed to minimize also the power consumption. The proposed power-aware test data compression technique is applied to the ISCAS'89 and ITC'99 benchmark circuits and on a number of industrial circuits. Results show that up to 20x reduction in test data volume and 95% test power reduction can be obtained simultaneously.
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00116832
Contributor : Martine Peridier <>
Submitted on : Tuesday, November 28, 2006 - 11:41:14 AM
Last modification on : Saturday, November 28, 2020 - 3:46:04 PM

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Nabil Badereddine, Zhanglei Wang, Patrick Girard, Krishnendu Chakrabarty, Arnaud Virazel, et al.. Power-Aware Test Data Compression for Embedded IP Core. 15th IEEE Asian Test Symposium (ATS), Nov 2006, Fukuoka, Japan. pp.5-10, ⟨10.1109/ATS.2006.66⟩. ⟨lirmm-00116832⟩

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