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A Gated Clock Scheme for Low Power Testing of Logic Cores

Abstract : Test power is now a big concern in large core-based systems. In this paper, we present a general approach for minimizing power consumption during test of integrated circuits or embedded cores. The proposed low power/energy technique is based on a gated clock scheme that can be used in a test-per-scan or a test-per-clock environment. The idea is to reduce the clock rate on the scan path (test-per-scan) or the test pattern generator (test-per-clock) without increasing the test time. Numerous advantages can be found in applying such a technique.
Keywords : Scan-Path Test Low-power
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Contributor : Christian Landrault Connect in order to contact the contributor
Submitted on : Monday, March 5, 2007 - 1:25:05 PM
Last modification on : Thursday, August 11, 2022 - 4:04:22 PM

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Christian Landrault, Yannick Bonhomme, Arnaud Virazel, Patrick Girard, Loïs Guiller, et al.. A Gated Clock Scheme for Low Power Testing of Logic Cores. Journal of Electronic Testing: : Theory and Applications, Springer Verlag, 2006, 22 (1), pp.89-99. ⟨10.1007/s10836-006-6259-1⟩. ⟨lirmm-00134766⟩



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