Abstract : Test power is now a big concern in large core-based systems. In this paper, we present a general approach for minimizing power consumption during test of integrated circuits or embedded cores. The proposed low power/energy technique is based on a gated clock scheme that can be used in a test-per-scan or a test-per-clock environment. The idea is to reduce the clock rate on the scan path (test-per-scan) or the test pattern generator (test-per-clock) without increasing the test time. Numerous advantages can be found in applying such a technique.
https://hal-lirmm.ccsd.cnrs.fr/lirmm-00134766
Contributeur : Christian Landrault
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Soumis le : lundi 5 mars 2007 - 13:25:05
Dernière modification le : jeudi 24 mai 2018 - 15:59:24
Christian Landrault, Yannick Bonhomme, Arnaud Virazel, Patrick Girard, Lois Guiller, et al.. A Gated Clock Scheme for Low Power Testing of Logic Cores. Journal of Electronic Testing, Springer Verlag, 2006, 22 (1), pp.89-99. 〈lirmm-00134766〉
