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A Gated Clock Scheme for Low Power Testing of Logic Cores

Christian Landrault 1 Yannick Bonhomme 1, 2 Arnaud Virazel 3 Patrick Girard 3 Loïs Guiller 4 Serge Pravossoudovitch 3
1 LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
2 LIST - Laboratoire d'Intégration des Systèmes et des Technologies
3 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
4 Synopsys Inc.
Abstract : Test power is now a big concern in large core-based systems. In this paper, we present a general approach for minimizing power consumption during test of integrated circuits or embedded cores. The proposed low power/energy technique is based on a gated clock scheme that can be used in a test-per-scan or a test-per-clock environment. The idea is to reduce the clock rate on the scan path (test-per-scan) or the test pattern generator (test-per-clock) without increasing the test time. Numerous advantages can be found in applying such a technique.
Keywords : Scan-Path Low-power Test
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Journal articles
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00134766
Contributor : Christian Landrault <>
Submitted on : Monday, March 5, 2007 - 1:25:05 PM
Last modification on : Monday, February 10, 2020 - 6:12:33 PM

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CNRS | SYSMIC | LIRMM | CEA | DRT | LIRMM_MIC | MIC | MIPS | UNIV-MONTPELLIER | LIST

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Christian Landrault, Yannick Bonhomme, Arnaud Virazel, Patrick Girard, Loïs Guiller, et al.. A Gated Clock Scheme for Low Power Testing of Logic Cores. Journal of Electronic Testing, Springer Verlag, 2006, 22 (1), pp.89-99. ⟨10.1007/s10836-006-6259-1⟩. ⟨lirmm-00134766⟩

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