Fault diagnosis is important in improving the design process and the manufacturing yield of nanometer circuits. It is however a challenging problem as today's complex defects lead to an explosion of the diagnosis solution space with the increasing number of possible fault locations and fault models. Our goal in this study consists in developing a new diagnosis method targeting almost all the nanometer defects in an unified manner (stuck-at, delay, open, stuck-on/open, short, resistive opens or shorts). The context of this study can be either external scan testing or scan-based BIST where time or space compaction is normally applied to test responses. Only logic cores are assumed as circuit under test/diagnosis in this study.