Logic Errors in CMOS Circuits due to Simultaneous Switching Noise - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Conference Poster Year : 2007
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lirmm-00154744 , version 1 (14-06-2007)

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  • HAL Id : lirmm-00154744 , version 1

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Florence Azaïs, Laurent Larguier, Michel Renovell. Logic Errors in CMOS Circuits due to Simultaneous Switching Noise. ETS: European Test Symposium, May 2007, Freiburg, Germany. 12th IEEE European Test Symposium, pp.59-64, 2007. ⟨lirmm-00154744⟩
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