DERRIC: A Tool for Unified Logic Diagnosis

Abstract : This paper presents DERRIC (Diagnosis of logic ERRors in VLSI Integrated Circuits), a diagnostic tool targeting most of the fault models used in practice today. This tool is intended to be used to diagnose faulty behaviors in nanometric circuits for which the classical stuck-at fault model is far to cover all the realistic failures. The underlying method of DERRIC is based on the Effect-Cause approach which relies on the two following main operations. The first one is based on critical path tracing (CPT) that consists in identifying critical lines in the Circuit Under Test (CUT) which can be the source of observed errors. The second one consists in allocating a set of possible fault models to each critical line, so that root causes of failures can be finally determined. The main advantage of this method is that it does not need to explicitly consider each fault model during the diagnosis process. Experiments on ISCAS'85 and ITC'99 benchmarks show the efficiency of the proposed tool in terms of diagnosis resolution.
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Communication dans un congrès
ETS: European Test Symposium, May 2007, Freiburg, Germany. 12th IEEE European Test Symposium, pp.13-18, 2007, 〈10.1109/ETS.2007.16〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00155993
Contributeur : Martine Peridier <>
Soumis le : mardi 19 juin 2007 - 16:04:41
Dernière modification le : jeudi 24 mai 2018 - 15:59:24

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Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Alexandre Rousset, et al.. DERRIC: A Tool for Unified Logic Diagnosis. ETS: European Test Symposium, May 2007, Freiburg, Germany. 12th IEEE European Test Symposium, pp.13-18, 2007, 〈10.1109/ETS.2007.16〉. 〈lirmm-00155993〉

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