A Digitally Testable Capacitance-Insensitive Mixed-Signal Filter

Erik Schuler 1 Marcelo Negreiros 1 Pascal Nouet 2 Luigi Carro 1
2 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : One of the main problems when developing analog filters in VLSI is to achieve high accuracy regarding the cutoff frequency. This is mainly due to the difficulty in obtaining accurate time constants. Testing of such filters is also challenging, in the sense that special equipment is required. Small deviations in the resistor or capacitor values may lead to a very high mismatch between the expected and the achieved cutoff frequency. Although switched-capacitor or active-transistor techniques may produce good results, the cost to use such approaches becomes another limiting factor, and only increases the tester needs. In this work, we present the development of an analog FIR filter, which does not use passive components to tune the cutoff frequency or the quality factor. Instead, the filter coefficients and the input signal are represented in a bit stream fashion, and are digitally processed, thus avoiding the use of expensive analog-to- digital converters. The impact of this filter architecture on test cost and possible design-for-test techniques are discussed in this paper.
Type de document :
Communication dans un congrès
ETS: European Test Symposium, May 2007, Freiburg, Germany. 12th IEEE European Test Symposium, pp.21-26, 2007, 〈10.1109/ETS.2007.6〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00158154
Contributeur : Martine Peridier <>
Soumis le : jeudi 28 juin 2007 - 10:40:36
Dernière modification le : jeudi 24 mai 2018 - 15:59:24

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Erik Schuler, Marcelo Negreiros, Pascal Nouet, Luigi Carro. A Digitally Testable Capacitance-Insensitive Mixed-Signal Filter. ETS: European Test Symposium, May 2007, Freiburg, Germany. 12th IEEE European Test Symposium, pp.21-26, 2007, 〈10.1109/ETS.2007.6〉. 〈lirmm-00158154〉

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