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An On-Line Fault Detection Scheme for SBoxes in Secure Circuits

Giorgio Di Natale 1 Marie-Lise Flottes 1 Bruno Rouzeyre 1
1 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : In this paper we propose an on-line fault detection architecture for bijective Substitution Boxes used in cryptographic circuits. Concurrent fault detection is important not only to protect the encryption/decryption process from random and production faults, it also protects the system against side-channel attacks, in particular those based on fault injection. We will prove that our solution is very effective while keeping the area overhead very low. Besides, we will analyze the correlation between the information processed by the circuit and the power consumption in order to asses the quality of the solution with respect to other side channel attacks such as Power Analysis techniques.
Keywords : Security AES Fault detection
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Conference papers
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00163244
Contributor : Giorgio Di Natale <>
Submitted on : Thursday, September 6, 2007 - 2:18:02 PM
Last modification on : Tuesday, September 1, 2020 - 11:32:04 AM

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CNRS | SYSMIC | LIRMM | LIRMM_MIC | MIC | MIPS | UNIV-MONTPELLIER

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Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. An On-Line Fault Detection Scheme for SBoxes in Secure Circuits. IOLTS: International On-Line Testing Symposium, Jul 2007, Heraklion, Crete, Greece. pp.57-62, ⟨10.1109/IOLTS.2007.16⟩. ⟨lirmm-00163244⟩

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