Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC

Abstract : This paper proposes an analytical method to assess the soft-error rate (SER) in the early stages of a System-on-Chip (SoC) platform-based design methodology. The proposed method gets an executable UML (Unified Modeling Language) model of the SoC and the raw soft-error rate of different parts of the platform as its inputs. Soft-errors on the design are modeled by disturbances on the value of attributes in the classes of the UML model and disturbances on opcodes of software cores. The Dynamic behavior of each core is used to determine the propagation probability of each variable disturbance to the core outputs. Furthermore, the SER and the execution time of each core in the SoC and a Failure Modes and Effects Analysis (FMEA) that determines the severity of each failure mode in the SoC are used to compute the System-Failure Rate (SFR) of the SoC.
Mots-clés : SoC Failure Rate SEU
Type de document :
Poster
IEEE. IOLTS'07: International On-Line Testing Symposium, Jul 2007, Heraklion, Crete, Greece, pp.205-206, 2007
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00163343
Contributeur : Giorgio Di Natale <>
Soumis le : mardi 17 juillet 2007 - 12:22:04
Dernière modification le : jeudi 24 mai 2018 - 15:59:24

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  • HAL Id : lirmm-00163343, version 1

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Mohammad Hosseinabady, M. H. Neishaburi, Zainalabedin Navabi, Alfredo Benso, Stefano Di Carlo, et al.. Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC. IEEE. IOLTS'07: International On-Line Testing Symposium, Jul 2007, Heraklion, Crete, Greece, pp.205-206, 2007. 〈lirmm-00163343〉

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