Improving NoC-based Testing Through Compression Schemes
Résumé
The effectiveness of the NoC reuse during test is very dependent on the number of test interfaces with the tester. This paper proposes a test scheduling method based on the use of a compression scheme to increase the number of test interfaces with the tester (thus increasing test parallelism) while still reusing available SoC pins and tester channels. We show that the combined approach allows test time minimization with minimal area overhead for systems with very few test interfaces.
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DATE07WS_NoC_Compress.pdf (56.34 Ko)
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NoCCompression_-_FINAL.ppt (977.5 Ko)
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