Temperature and Voltage Aware Timing Analysis

Benoit Lasbouygues 1 R. Wilson 1 Nadine Azemard 2 Philippe Maurine 2
2 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : In the nanometer era, the physical verification of CMOS digital circuit becomes a complex task. Designers must account of new factors that impose a significant change in validation methods. One of these major changes in timing verification to handle process variation lies in the progressive development of statistical static timing engines. However the statistical approach cannot capture accurately the deterministic variations of both the voltage and temperature variations. Therefore, we define a novel method, based on non-linear derating coefficients, to account of these environmental variations. Based on temperature and voltage drop CAD tool reports, this method allows computing the delay of logical paths considering more realistic operating conditions for each cell. Application is given to the analysis of voltage drop effects on timings.
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Article dans une revue
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE, 2007, 26 (4), pp.801-815
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Soumis le : mardi 11 décembre 2007 - 14:51:46
Dernière modification le : jeudi 11 janvier 2018 - 06:27:18
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  • HAL Id : lirmm-00178921, version 1

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Benoit Lasbouygues, R. Wilson, Nadine Azemard, Philippe Maurine. Temperature and Voltage Aware Timing Analysis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE, 2007, 26 (4), pp.801-815. 〈lirmm-00178921〉

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