Temperature and Voltage Aware Timing Analysis - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Journal Articles IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Year : 2007

Temperature and Voltage Aware Timing Analysis

Abstract

In the nanometer era, the physical verification of CMOS digital circuit becomes a complex task. Designers must account of new factors that impose a significant change in validation methods. One of these major changes in timing verification to handle process variation lies in the progressive development of statistical static timing engines. However the statistical approach cannot capture accurately the deterministic variations of both the voltage and temperature variations. Therefore, we define a novel method, based on non-linear derating coefficients, to account of these environmental variations. Based on temperature and voltage drop CAD tool reports, this method allows computing the delay of logical paths considering more realistic operating conditions for each cell. Application is given to the analysis of voltage drop effects on timings.
Fichier principal
Vignette du fichier
maurine_azemard.pdf (266.78 Ko) Télécharger le fichier
Loading...

Dates and versions

lirmm-00178921 , version 1 (11-12-2007)

Identifiers

Cite

Benoit Lasbouygues, Robin P. Wilson, Nadine Azemard, Philippe Maurine. Temperature and Voltage Aware Timing Analysis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2007, 26 (4), pp.801-815. ⟨10.1109/TCAD.2006.884860⟩. ⟨lirmm-00178921⟩
85 View
510 Download

Altmetric

Share

Gmail Facebook X LinkedIn More