The migration of transistors in the very deep submicron region has allowed the integration of billions of transistors on a single chip. However, this relentless march has caused the rapid emergence of variability problems, which have adverse effects on the circuit's performance. This paper highlights the importance of taking into account process variability aspects in the design of an eSRAM for reducing the excessive design margin, introduced by the corner analysis method. We show that the sensitivity dispersions of the memory to process variations can be mitigated through the use of an appropriate dummy bit line driver (DBD). This component is in fact an essential element in a self-timed memory. We made use of the DBD in a 256kb SRAM in 90nm technology process.