Skip to Main content Skip to Navigation
Conference papers

Analyzing the Logic Behavior of Digital CMOS Circuits in Presence of Simultaneous Switching Noise

Abstract : This paper analyzes the logic errors in digital circuits due to the presence of Simultaneous Switching Noise (SSN). It is demonstrated that 2 conditions must be fulfilled in order to guarantee the correct logic behaviour of a digital circuits. The first condition called ‘Minimum Switch Condition' is proved to be fulfilled whatever the amount of SSN in the power and ground lines. The second condition called ‘Signal Coherence Condition' is proved to be fulfilled within power coherent logic blocks. However the interface between non-coherent logic blocks may originate logic dysfunction
Complete list of metadatas

https://hal-lirmm.ccsd.cnrs.fr/lirmm-00199261
Contributor : Florence Azais <>
Submitted on : Saturday, January 21, 2017 - 9:29:07 PM
Last modification on : Friday, July 20, 2018 - 12:34:01 PM
Long-term archiving on: : Saturday, April 22, 2017 - 1:07:51 PM

File

3analysing.pdf
Files produced by the author(s)

Identifiers

  • HAL Id : lirmm-00199261, version 1

Collections

Citation

Florence Azaïs, Laurent Larguier, Michel Renovell. Analyzing the Logic Behavior of Digital CMOS Circuits in Presence of Simultaneous Switching Noise. LATW: Latin American Test Workshop, Mar 2007, Cuzco, Peru. ⟨lirmm-00199261⟩

Share

Metrics

Record views

178

Files downloads

260