Analyzing the Logic Behavior of Digital CMOS Circuits in Presence of Simultaneous Switching Noise

Abstract : This paper analyzes the logic errors in digital circuits due to the presence of Simultaneous Switching Noise (SSN). It is demonstrated that 2 conditions must be fulfilled in order to guarantee the correct logic behaviour of a digital circuits. The first condition called ‘Minimum Switch Condition' is proved to be fulfilled whatever the amount of SSN in the power and ground lines. The second condition called ‘Signal Coherence Condition' is proved to be fulfilled within power coherent logic blocks. However the interface between non-coherent logic blocks may originate logic dysfunction
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Communication dans un congrès
LATW: Latin American Test Workshop, Mar 2007, Cuzco, Peru. 8th IEEE Latin American Test Workshop, 2007
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00199261
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  • HAL Id : lirmm-00199261, version 1

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Florence Azaïs, Laurent Larguier, Michel Renovell. Analyzing the Logic Behavior of Digital CMOS Circuits in Presence of Simultaneous Switching Noise. LATW: Latin American Test Workshop, Mar 2007, Cuzco, Peru. 8th IEEE Latin American Test Workshop, 2007. 〈lirmm-00199261〉

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