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InP HBT XOR and Phase-Detector for 40Gbit/s Clock and Data Recovery (CDR)

Vincent Puyal 1 Agnieszka Konczykowska 2 Muriel Riet 2 Serge Bernard 3 Pascal Nouet 3 Jean Godin 2
1 LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
2 III-V Lab - Alcatel-Thalès III-V lab
3 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : High-speed XOR and phase-detector circuit necessary for clock and data recovery were designed and fabricated in a self-aligned InP DHBT technology. In the paper, we present the circuit design with the special highlight of the architecture choice and design challenges. Measurements results of fabricated circuits are shown.
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Conference papers
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00202634
Contributor : Martine Peridier <>
Submitted on : Monday, January 7, 2008 - 3:25:03 PM
Last modification on : Tuesday, January 5, 2021 - 4:00:01 PM

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CNRS | SYSMIC | LIRMM | LIRMM_MIC | MIC | MIPS | UNIV-MONTPELLIER

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Vincent Puyal, Agnieszka Konczykowska, Muriel Riet, Serge Bernard, Pascal Nouet, et al.. InP HBT XOR and Phase-Detector for 40Gbit/s Clock and Data Recovery (CDR). MIKON: Microwaves, Radar & Wireless Communications, May 2006, Paris, France. pp.1115-1118, ⟨10.1109/MIKON.2006.4345382⟩. ⟨lirmm-00202634⟩

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