InP HBT XOR and Phase-Detector for 40Gbit/s Clock and Data Recovery (CDR)

Abstract : High-speed XOR and phase-detector circuit necessary for clock and data recovery were designed and fabricated in a self-aligned InP DHBT technology. In the paper, we present the circuit design with the special highlight of the architecture choice and design challenges. Measurements results of fabricated circuits are shown.
Type de document :
Communication dans un congrès
MIKON: Microwaves, Radar & Wireless Communications, May 2006, Paris, France. pp.1115-1118, 2006, 〈10.1109/MIKON.2006.4345382〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00202634
Contributeur : Martine Peridier <>
Soumis le : lundi 7 janvier 2008 - 15:25:03
Dernière modification le : jeudi 24 mai 2018 - 15:59:24

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Vincent Puyal, Agnieszka Konczykowska, Muriel Riet, Serge Bernard, Pascal Nouet, et al.. InP HBT XOR and Phase-Detector for 40Gbit/s Clock and Data Recovery (CDR). MIKON: Microwaves, Radar & Wireless Communications, May 2006, Paris, France. pp.1115-1118, 2006, 〈10.1109/MIKON.2006.4345382〉. 〈lirmm-00202634〉

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