General Representation of CMOS Structure Transition time for Timing Library Representation

Philippe Maurine 1 Nadine Azemard 1, * Daniel Auvergne 2
* Auteur correspondant
1 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : Nonzero signal rise and fall times significantly contribute to gate propagation delay. Designers must accurately consider them when defining timing library format. Based on a design oriented macromodel of the timing performance of complementary metal-oxide semiconductor (CMOS) structures, a general representation of transition times allowing fast and accurate cell performance evaluation is presented. This representation is validated comparing calculated gate input-output transition time values with respect to standard lookup representation obtained from HSPICE simulations (BSIM3, v.3, level 69, 0.25 μm process).
Type de document :
Article dans une revue
Electronics Letters, IET, 2002, 38 (4), pp.175-177
Liste complète des métadonnées

https://hal-lirmm.ccsd.cnrs.fr/lirmm-00239318
Contributeur : Nadine Azemard <>
Soumis le : mardi 5 février 2008 - 14:30:34
Dernière modification le : mercredi 17 octobre 2018 - 17:20:02

Identifiants

  • HAL Id : lirmm-00239318, version 1

Citation

Philippe Maurine, Nadine Azemard, Daniel Auvergne. General Representation of CMOS Structure Transition time for Timing Library Representation. Electronics Letters, IET, 2002, 38 (4), pp.175-177. 〈lirmm-00239318〉

Partager

Métriques

Consultations de la notice

66